The present invention relates to communication networks and more particularly to a method and system for exchanging information, under the form of fixed-size cells, on ports and within data flow of a very high-speed switch fabric.
The advent of very high-speed communication links (especially in the use of fiberoptical connections), along with the demand for integrating different kinds of communication traffic and services (voice, data, image, video, high quality sound, multimedia) over a single type of network, has led the telecommunications industry to develop a concept called xe2x80x9cBroadband Integrated Services Digital Networkxe2x80x9d or B-ISDN. Recommendations to standardize this concept have been issued by the International Telecommunications Union Standardization Sector (ITU-T). The technology selected to deliver it is called Asynchronous Transfer Mode or ATM. Its chief characteristic is that information is transferred under the form of small fixed-size packets or cells as a compromise between the diverging requirements for transporting large data files or digitally coded voice. All this is described, for example, in a book by Raif O. Onvural, entitled xe2x80x9cAsynchronous Transfer Mode Networksxe2x80x9d, Second Edition, Artech House Publishers, 1995. The key factor which makes ATM possible is the ability to build switching devices, hereafter called switch or switch fabric, which processes cells at a very high rate.
The amount of data to be moved through switches is increasing dramatically to cope with the exponential demand for bandwidth so as to exchange more and more information, in digital form, ranging from simple data files to voice, pictures and video. If, at the same time, the technology to implement the core of switches is progressing at an equivalent pace and is definitively able to easily match the bandwidth demand as far as internal processing speed is concerned, giving access to this processing capability is becoming the bottleneck. There are serious reasons which inhibit the ability to increase bandwidth on the input and output points of a switch at the same rate, namely the ports, and more generally to gain access to the components of a switch fabric:
One traditional way of boosting access throughput to a device is to increase parallelization; i.e., the number of wires and I/Os implementing the bus to access it. There is soon a limitation for a switch having many IN/OUT ports. Typically, 16xc3x9716 switches are required to cope with today""s network complexity multiplying accordingly the total number of module I/Os and board wires.
The other solution is to increase the switching speed of the ports, thus allowing to transport the same quantity of data, per unit of time, on fewer wires. The limit in this case is due to the fact that the drivers located at the periphery of the modules implementing the switch fabric are made slower than imbedded logic because they have to drive higher value capacitors requiring switching more current through the parasitic inductances of the components, thus creating the well-known simultaneous switching problem which practically set the speed at which they can be toggled.
Then, implementing an access to the many ports of a switch and moving data through the switch fabric while achieving performances measured in tenths of Gigabits per second requires that both packaging and I/O performance be pushed to their limits. This makes impracticable traditional methods of exchanging data between a peripheral device and its processing unit which translates, in the field of communications more specifically considered here, into the exchange of data between an adapter, in charge of interfacing a high-speed communication line and the device that collects and dispatches the information at a network node, namely the switch. All traditional methods are making use of extra signals allowing to implement a simple protocol. A typical method, proposed by the ATM forum organization and known under the acronym of UTOPIA, described for instance in xe2x80x98UTOPIA Level 2 specification, af-phy-0039.00, June 1995xe2x80x99, uses a companion clock to sample the data on a 1- or 2-byte bus along with a delimiter indicating the start of cell (SOC). This scheme works well up to a speed where the signal skews introduced by the chips, modules and board technologies presently in use are low with respect to the data rate to achieve. Moreover, even if skews are possibly accommodated, the use of two extra signals per port, in every direction, may not be compatible with the I/O limitation here above mentioned.
A standard application of the UTOPIA bus uses a clock at 33 Mhz on a 1-byte bus allowing to have one ATM cell (53 bytes) exchanged every 1.6 xcexcseconds which is sufficient to cope with adapters concentrating traffic on the very common third level of the Synchronous Optical Network (SONET) US hierarchy (OC-3 at 155 Mbps) or its equivalent European counterpart, the first level of the Synchronous Digital Hierarchy (SDH), called STM-1, which calls for a max processing capability of up to one cell every 2.8 xcexcseconds. However, this becomes definitively not adequate whenever switches are able to sustain throughput measured in tenths of Gigabits per second aggregating traffic from adapter ports, each running at speed one order of magnitude higher than OC-3 and more, reaching the OC-48 or STM-16 level; i.e., 2.4 Gigabit/sec per port. At these speeds, relying on a Start of Cell signal and a companion clock to retrieve data is just not a reliable working solution.
More particularly, the invention provides, in a communication network, in which a switch is capable of switching fixed-size incoming cells, a method for giving access to ports of the switch comprising the steps of splitting incoming cells over a plurality of physical units; segmenting incoming cells into fixed-size data logical units; generating fixed-size idle logical units, of the same size as the data logical units to fill traffic for recovering, at receive side, a self-sampling clock for the physical units; inserting a delimiter within each idle logical unit, for cell delineation, said delimiter comprising two subfields, a first subfield for acquiring synchronization computed only from the delimiter itself and a second subfield computed continuously on the flow of bits for further asserting and monitoring synchronization.
The invention also provides for a system implementing the above method.